This article is compiled by Semiconductor Industry Horizons (ID: ICVIEWS) from semiengineering

As the advantages of planar scaling diminish, foundry competition in the 3D field and new technologies is intensifying.

The three leading-edge foundries — Intel, Samsung and TSMC — have begun filling in some key parts of their roadmaps, adding aggressive delivery dates for future generations of chip technology and laying the groundwork for significantly higher performance and shorter lead times for custom designs.

Unlike in the past, when there was a single industry roadmap dictating how to proceed to the next process node, today the three largest foundries are increasingly carving their own paths. They are all heading in the same general direction, with 3D transistors and packaging, a range of supporting and scaling technologies, and a larger and more diverse ecosystem. But some key differences are emerging in their approaches, architectures, and third-party support.

Roadmaps for all three show transistor scaling continuing at least into the 18/16/14 angstrom range, with a possible move from nanosheet and forksheet FETs to complementary FETs (CFETs) at some point in the future. The key drivers are AI/machine learning and the explosion of data that needs to be processed, which in most cases will involve arrays of processing elements, typically with high levels of redundancy and homogeneity to achieve higher yields.

In other cases, these designs may contain dozens or hundreds of chips, some for specific data types and others for more general processing. The chips can be mounted on a substrate in a 2.5D configuration, an approach that has gained favor in data centers because it simplifies the integration of high-bandwidth memory (HBM) and has also been promoted in mobile devices, which also include other functions such as image sensors, power supplies and additional digital logic for non-critical functions. All three foundries are working on full 3D-ICs. And there will also be hybrid options available, in which logic is stacked on logic and mounted on a substrate but separated from other functions to minimize physical effects such as heat - this heterogeneous configuration is called 3.5D and 5.5D.

Rapid and mass customization

One of the biggest changes is bringing domain-specific designs to market faster than in the past. This may sound mundane, but for many leading-edge chips it is a competitive necessity, and it requires fundamental changes to the way chips are designed, manufactured and packaged. Making this work requires a combination of standards, innovative connectivity schemes and multiple engineering disciplines that have had limited or no interaction in the past.

Sometimes referred to as “mass customization,” it includes the usual power, performance, and area/cost (PPA/C) trade-offs, along with rapid assembly options. This is the promise of heterogeneous chip components, and from a scaling perspective, it marks the next phase of Moore’s Law. For more than a decade, the entire semiconductor ecosystem has been gradually laying the foundation for this shift.

But getting heterogeneous chips—essentially hardened IP from multiple vendors and foundries—to work together is both a necessary and daunting engineering challenge. The first step is connecting the chips together in a consistent way that achieves predictable results, and this is where the foundries are investing a lot of effort, particularly in the Universal Chip Interconnect Express (UCIe) and Bundle of Wires (BoW) standards. While this connectivity is a key requirement for all three, it is also one of the main areas of divergence.

Until 3D-ICs are fully integrated, Intel’s foundry solution is to develop what industry insiders call chip “sockets.” Rather than characterizing each chip for the commercial market, the company defines the specifications and interfaces so that chip vendors can develop these tiny, limited-function chips to meet those specifications. This solves a big hurdle in the commercial chip market. From data speeds to heat and noise management, all the parts need to work together.

Intel’s approach relies heavily on its Embedded Multi-die Interconnect Bridge (EMIB), which it first introduced in 2014. “What’s really cool about the EMIB base is that you can add as many chips as you want,” said Lalitha Immaneni, vice president of technology development at Intel. “We have no limit on the amount of IP that can be used in the design, and it doesn’t increase the size of the interposer, so it’s cost-effective and process-agnostic. We provide a package assembly design kit, which is like a traditional assembly PDK. We give them the design rules, the reference flow, and tell them the allowed structures. It also gives them any collateral that we need to take it into assembly.”

Depending on the design, there can be multiple EMIBs in a package, supplemented by thermal interface materials (TIMs) to dissipate heat that may be trapped within the package. TIMs are typically pads designed to conduct heat away from the source, and are becoming more common as the amount of computing within a package increases and substrates become thinner to reduce the distance signals need to travel.

But thinner substrates dissipate heat less effectively, which can lead to thermal gradients that are workload-dependent and therefore difficult to predict. Removing this heat may require a TIM, an additional heat sink, or even more exotic cooling methods such as microfluidics.

TSMC and Samsung both offer bridges. Samsung embeds bridges in the RDL (an approach called 2.3D or I-Cube ETM) and uses them to connect subsystems to these bridges to speed up the life of the silicon. Some of the integration work will be done up front in known good modules rather than relying on a socket approach.

“Combining two, four or eight CPUs into a system is something that very mature customers know how to do,” said Arm CEO Rene Haas during a keynote at a recent Samsung Foundry event. “But if you want to build an SoC that has 128 CPUs connected to it,Neural Networks"If you have a CPU that's built in, a memory structure, an interrupt controller that interfaces with the NPU, an off-chip bus that connects to another chip, then that's a lot of work. Over the last year and a half, we've seen a lot of people building these complex SoCs who want more from us."

Samsung has also been forming alliances of small chip suppliers to target specific markets. The initial concept is for one company to make I/O chips, another to make interconnects, and a third to make logic, and when that approach proves viable, others will join in to give customers more options.

TSMC has tried a number of different approaches, including RDL and non-RDL bridging, fan-out, 2.5D chip-on-wafer-on-substrate (CoWoS), and system-on-integrated-chip (SoIC), a 3D-IC concept in which chips are packaged and stacked within a substrate using very short interconnects. In fact, TSMC has process design kits for nearly every application and has been actively creating assembly design kits for advanced packaging, including reference designs to go with them.

The challenge is that foundry customers willing to invest in these complex packages increasingly want highly customized solutions. To achieve this, TSMC has introduced a new language called 3Dblox, a top-down design approach that merges physical and connectivity structures, allowing assertions to be applied between the two. This sandbox approach allows customers to leverage any of its packaging methods - InFO, CoWoS and SoIC. It is also critical to TSMC's business model, as the company is the only pure-play foundry of the three companies - although Intel and Samsung have both distanced themselves from the foundry business in recent months.

“We start with the concept of modularity,” said Jim Chang, TSMC vice president of advanced technology and mask engineering, during a presentation when 3Dblox was first introduced in 2023. “We can use this language syntax plus assertions to build a complete 3D-IC stack.”

Chang said the reason for this is a lack of consistency between physical and connectivity design tools, but added that once the approach is developed, it also makes it possible to reuse chips in different designs because most of the features are already well defined and the designs are modular.

Figure 1: TSMC’s 3Dblox approach. Source: TSMC

Samsung followed with its own system description language, 3DCODE, in December 2023. Both Samsung and TSMC claim their languages ​​are standards, but they are more like new foundry rule platforms because the languages ​​are unlikely to be used outside their own ecosystems. Intel's 2.5D approach does not require a new language because the rules are determined by the socket specification, which allows some customization at the expense of faster time to market and a simpler approach for chip developers.

Chip Challenge

Chips have obvious advantages. They can be designed independently at any reasonable process node, which is particularly important for analog functions. But how to put the pieces together and produce predictable results has been a major challenge. DARPA's original Lego-like architecture turned out to be much more complex than originally envisioned, requiring a lot of sustained effort from the ecosystem to make it a reality.

Chipsets need to be precisely synchronized so that critical data can be processed, stored, and retrieved without delay. Otherwise, timing issues can arise where one calculation is either delayed or out of sync with the others, causing latency and potential deadlocks. In mission- or safety-critical applications, even a single second lost can have serious consequences.

Simplifying the design process is an extremely complex task, especially for domain-specific designs because there are no unified standards. The goal of these three foundries is to provide more options for companies developing high-performance, low-power chips. It is estimated that about 30% to 35% of all leading-edge designs are currently handled by large system companies such as Google, Meta, Microsoft and Tesla. The economics of leading-edge chip and package design have undergone major changes, and the PPA/C formula and trade-offs have also undergone major changes.

Chips companies develop for these systems may not be sold commercially. So if they can achieve higher performance per watt, the design and manufacturing costs can be offset by reduced cooling power and higher utilization—and potentially fewer servers. The opposite is true for chips sold into mobile devices and commercial servers, where high development costs can be amortized through high volumes of production. Custom design in advanced packaging makes economic sense for both, but for very different reasons.

Zoom in, zoom out, and zoom out

It is estimated that there will be multiple types of processors in these complex chiplet systems, some highly specialized and others more general purpose. Due to limited power budgets, at least some of them will likely be developed on the most advanced process nodes. Advanced nodes still offer higher energy efficiency, which allows more transistors to be packed into the same area to increase performance. This is critical for AI/ML applications because more multiplication/accumulation operations need to be performed in a highly parallel configuration to process more data faster. Smaller transistors offer higher energy efficiency, allowing more processing per square millimeter of silicon, but require changes to the gate structure to prevent leakage, which is why forksheet FETs and CFETs are coming.

In short, process leadership still has value. Being the first to market with a cutting-edge process is good for a business, but it’s just one piece of a larger puzzle. All three foundries have announced plans to move to angstrom-class processes. Intel plans to launch 18A this year, followed by 14A a few years later.

Figure 2: Intel's process roadmap. Source: Intel Foundry

At the same time, TSMC will add the A16 in 2027 (see Figure 3 below).

Figure 3: TSMC’s scaling roadmap into the Angstrom era. Source: TSMC

Samsung will increase resolution to 14 angstroms with its SF1.4 around 2027, apparently skipping 18/16 angstroms. (See Figure 4)

Figure 4: Samsung's process expansion roadmap. Source: Samsung Foundry

From a process node perspective, all three foundries are on the same track. But progress is no longer just about process nodes. There is a growing focus on latency and performance per watt in specific areas, and this is where the advantages of stacking logic in a true 3D-IC configuration come in, using hybrid bonds to connect the chips to the substrate and to each other. Moving electrons through wires on a planar chip is still fastest (assuming the signal doesn’t have to travel from one end of the chip to the other), but stacking transistors on top of other transistors is the next best option, and in some cases even better than a planar SoC because some vertical signal paths can be shorter.

In a recent presentation, Taejoong Song, vice president of foundry business development at Samsung Foundry, presented a roadmap that features logic stacking technology, where logic is mounted on a substrate, combining a 2nm (SF2) chip with a 4nm (SF4X) chip, both mounted on another substrate. This is basically a 3D-IC on a 2.5D package, which is the 3.5D or 5.5D concept mentioned earlier. Song said the foundry will start stacking SF1.4 on SF2P in 2027. What is particularly attractive about this approach is the possibility of heat dissipation. By separating logic from other functions, heat can be discharged from the stacked chips through the substrate or any of the five exposed surfaces.

Figure 5: Samsung's 3D-IC architecture for AI. Source: Samsung

Meanwhile, Intel will use its Foveros Direct 3D to stack logic on logic, either face-to-face or face-to-face. According to Intel's latest white paper, this approach allows chips or wafers from different foundries to be connected with the bandwidth determined by the copper via pitch. The first generation will use a 9µm copper pitch, while the second generation will use a 3µm pitch, the paper states.

Figure 6: Intel's Foveros Direct 3D. Source: Intel

“True 3D-ICs come with Foveros and then hybrid keys,” Intel’s Immaneni said. “You can’t go the traditional design route and put everything together and then do validation and then find out, ‘Oops, I have a problem.’ You can’t do that anymore because you’re going to impact your time to market. So you really want to provide a sandbox to make it predictable. But even before I get into this detailed design environment, I want to run my mechanical/electrical/thermal analysis. I want to look at connectivity so I don’t have opens and shorts. The burden of 3D-IC is more on the code design than the execution.”

Foveros allows active logic chips to be stacked on top of another active or passive chip and uses a base die to connect all the chips in the package at a 36-micron pitch. By leveraging advanced sorting techniques, Intel claims it can guarantee 99% known good chips and 97% post-assembly test yield.

Meanwhile, TSMC's CoWoS has been used by NVIDIA and AMD for advanced packaging of their AI chips. CoWoS is essentially a 2.5D approach that uses an interposer to connect the SoC and HBM memory through silicon vias. The company's plans for SoIC are more ambitious, packaging memory on logic along with other elements such as sensors in a 3D-IC at the front end of the production line. This can significantly reduce assembly time for multiple layers, size, and functionality. TSMC claims that its bonding scheme can achieve faster and shorter connections compared to other 3D-IC methods. A report said that Apple will use TSMC's SoIC technology starting next year, while AMD will expand its use of this method.

Other innovations

The availability of process and packaging technologies has opened the door to a wider range of competitive choices. Unlike in the past when chip roadmaps were defined by large chipmakers, equipment vendors, and EDA companies, the chiplet world gives end customers the tools to make these decisions. This is largely due to the difference between the number of functions that can be put into a package and the number of functions that can be put within the constraints of the SoC mask. Packages can be scaled horizontally or vertically as needed, and in some cases they can improve performance through vertical floorplanning.

But given the huge opportunities in the cloud and edge, especially as AI becomes more prevalent, the three major foundries and their ecosystems are racing to develop new capabilities and features. In some cases, this requires leveraging resources they already have. In other cases, it requires entirely new technologies.

Samsung, for example, has already begun to detail its custom HBM initiative, which includes a 3D DRAM stack with a configurable logic layer underneath. This is the second time this approach has been adopted. Back in 2011, Samsung and Micron jointly developed the Hybrid Memory Cube, which encapsulated the DRAM stack on the logic layer. After JEDEC made HBM a standard, HBM won the war and HMC basically disappeared. But there is nothing wrong with the HMC approach, it's just the wrong time.

Samsung plans to offer custom HBM in the new form factor as an option. Memory is one of the key factors that determine performance, and the ability to read and write and move data back and forth faster between memory and the processor can have a significant impact on performance and power consumption. If the memory is sized appropriately for a specific workload or data type, and if some of the processing can be done inside the memory module, so that less data needs to be moved, then these numbers can be significantly improved.

Figure 7: Samsung roadmap and innovation. Source: Semiconductor Engineering/MemCon 2024

Meanwhile, Intel has been working on a better way to power densely packed transistors, a problem that persists as transistor density and the number of metal layers increase. In the past, power was delivered from the top of the chip down, but two problems emerged at the most advanced nodes. One is the challenge of actually delivering enough power to each transistor. The second is noise, which can come from the power supply, the substrate, or electromagnetic interference. Without proper shielding—which becomes increasingly difficult at each new node as dielectrics and wires get thinner—noise can affect signal integrity.

Powering the chip through the back side can minimize such problems and reduce wiring congestion. But this also brings other challenges, such as how to drill holes in thinner substrates without damaging the structure. Intel has apparently solved these problems and plans to launch its PowerVia back-side power supply solution this year.

TSMC said it plans to implement backside power delivery for the A16 in 2026/2027. Samsung's timeline is roughly the same, with backside power delivery to be implemented in the SF2Z 2nm process.

Intel also announced plans for glass substrates, which offer better planarity and lower defectivity than CMOS. This is especially important at advanced nodes, where even nanometer-scale pits can cause problems. As with backside power, handling issues abound. The upside is that glass has the same coefficient of thermal expansion as silicon, so it is compatible with the expansion and contraction of silicon components like chips. After years of being ignored, glass is suddenly very attractive. In fact, TSMC and Samsung are both working on glass substrates, and the industry as a whole is starting to design with glass, handle it without breaking it, and inspect it.

At the same time, TSMC has placed a high priority on building an ecosystem and expanding its process offerings. Many industry insiders say TSMC's real advantage is its ability to provide process development kits for almost any process or package. The foundry produces about 90% of the world's most advanced chips, according to Nikkei. It also has the most advanced packaging experience, the largest and broadest ecosystem of all foundries, which is important.

This ecosystem is critical. The chip industry is so complex and diverse that no one company can do it all. The question going forward is how complete these ecosystems really are, especially if the number of processes continues to grow. For example, EDA vendors are essential enablers, and design teams need automation for any process or packaging approach to be successful. But the more process and packaging options there are, the harder it will be for EDA vendors to support every incremental change or improvement, and the lag time between announcement and delivery will likely be longer.

in conclusion

Recent supply chain glitches and geopolitics have convinced the US and Europe that they need to repatriate manufacturing and “relocate friendly.” Investments in semiconductor fabs, equipment, tools, and research are unprecedented. The impact on the big three foundries remains to be seen, but it is certainly providing some momentum for new technologies, such as co-packaged optics, a host of new materials, and cryogenic computing.

The impact of all these changes on market share is increasingly difficult to track. It’s no longer about which foundry makes chips at the smallest process node, or even how many chips are shipped. An advanced package might have dozens of chiplets. What really matters is the ability to deliver important solutions to customers quickly and efficiently. In some cases, the driver is performance per watt, while in other cases it may be time to results, with power consumption being a secondary consideration. In still other cases, it may be a feature set that only one leading foundry can offer in sufficient volume. But it’s clear that foundry competition is far more complex than ever before, and it’s getting more so. In this highly complex world, simple comparison metrics no longer apply.

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