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Applications such as artificial intelligence (AI) and high-performance computing (HPC) have driven a surge in demand for high-computing chips, and as Moore's Law approaches its limit, advanced packaging is gradually becoming the key to improving chip performance. Currently, many advanced packaging technologies such as 2.5D, 3D-IC, heterogeneous integration, and Chiplet help chip designers provide more functions in smaller, lower-power chips and achieve a leap in performance. However, these technological advances have also brought unprecedented challenges, and they have placed higher requirements on existing manufacturing processes, equipment, and materials.

More and more advanced packaging involves the so-called "middle-end" process between wafer manufacturing ("front-end") and chip packaging and testing ("back-end"), including redistribution wiring (RDL), bumping, through silicon via (TSV) and other process technologies, involving similar process steps as wafer manufacturing, such as lithography, development, etching, and stripping. Among them, lithography technology plays a vital role, and lithography equipment has been widely used in the production of flip-chip structure packaging bumping, RDL, 2.5D/3D packaging TSV, etc. in the field of advanced packaging.

Today, direct writing lithography has completely replaced traditional lithography in the field of board-level packaging and high-end IC substrate manufacturing; it has also begun to emerge in the fields of high-end display, advanced packaging and third-generation semiconductors. Under the tide of advanced packaging, the domestic direct writing lithography technology leader, Xinji Micro-Equipment, is bringing breakthrough changes to the industry with its excellent performance and innovative technical solutions.

Advanced packaging is coming, direct write lithography is emerging

Take TSMC's CoWoS, which has attracted much attention since last year, as an example. It is a 2.5D packaging technology that is a combination of CoW and oS. The chip is first connected to the silicon wafer through the Chip on Wafer (CoW) packaging process, and then the CoW chip is connected to the substrate (Substrate) to integrate into CoWoS. The core of this technology is to stack different chips on the same silicon interposer to achieve interconnection between multiple chips. In the silicon interposer, TSMC uses microbumps (μBmps), through silicon vias (TSV) and other technologies instead of traditional wire bonding for bare die connections, greatly improving the interconnection density and data transmission bandwidth. Depending on the interposer used, TSMC divides CoWoS packaging technology into three types: CoWoS-S (Silicon Interposer), CoWoS-R (RDL Interposer) and CoWoS-L (Local Silicon Interconnect and RDL Interposer).

For example, CoWoS is used to produce high-performance AI chips from companies such as Nvidia, AMD, Amazon, and Google. As the number of transistors in AI chips continues to increase, and because they are used in data centers and cloud computing, the size requirements are not high, so AI chips in the future are likely to become larger and larger. Currently, TSMC is using CoWoS packaging technology to develop AI chips that are larger than AMD's Instinct MI300X and Nvidia's B200, with a packaging area of ​​120mmx120mm.

Pan Changlong, sales director of Core Micro-Equipment Semiconductor, pointed out that TSMC currently mainly uses CoWoS-S. With the increasing number of large-area chip designs, more and more interposers, and larger mask sizes, when the interposer reaches more than four times the size of TSMC's largest reticle (1X reticle≈830mm²), which is 3.3 times higher than its current interposer, it will switch to CoWoS-L.

Pan Changlong, Sales Director of Xinji Micro-Equipment Pan Semiconductor

Data shows that the theoretical EUV reticle limit is 858mm² (26 mm x 33 mm), so a 5148 mm² SiP will be achieved by splicing six masks. Such a large interposer not only provides space for multiple large computing chiplets, but also leaves enough space for 12 stacks of HBM memory, which means a 12288-bit memory interface bandwidth of up to 9.8 TB/s. Building a 5148 mm² SiP is an extremely difficult task. The current Nvidia H100 accelerator, whose package spans multiple mask sizes across an interposer, costs as much as $30,000. Therefore, larger and more powerful chips may further increase packaging costs.

In addition to CoWoS-L, some chip design companies have also begun to study wafer-level systems (SoW). This type of design uses the entire wafer as a packaging unit. Logic, storage, and control-related chips need to be integrated through packaging. The RDL wiring will be quite complicated, and the number of RDL layers will become higher and higher.

Regarding the trends of these two advanced packaging technologies, Pan Changlong said that larger-area chip packaging will bring many challenges to the use of traditional stepper lithography machines.

One is the problem of mask splicing.As the package area increases, a single mask cannot cover the entire chip, and multiple masks need to be used and spliced. This increases the complexity of the manufacturing process and may cause alignment errors at the splicing point, affecting the performance and yield of the final product. In addition, the increase in package area may increase warping and defects in the production process, resulting in a decrease in yield. Especially in the mask splicing area, any slight error may affect the performance of the entire chip. With the integration of chips and the use of large-size wafers, the problem of wafer warpage has become increasingly severe and has become one of the main challenges affecting the reliability of advanced packaging.

Second, the design complexity increases and production efficiency decreases.Large-size package design requires more complex wiring and stacking technology. For example, the wiring of the RDL layer will be quite complex, and the number of layers will increase, which brings great challenges to both design work and manufacturing processes. In particular, large-size package design requires switching masks in the lithography machine to expose the same layer of lines. This frequent mask switching will reduce production efficiency and prolong the production cycle.

The third is the limitation of the equipment.Traditional stepper lithography equipment has a mask size of mostly 26×33mm², and may not have experience in dealing with problems such as warpage of large-size packages. Lithography of large-size packages requires equipment to be able to handle larger wafers/carriers and deal with problems such as warpage.

Pan Changlong said that in addition to wafer-level packaging such as CoWoS and SoW, FoPLP packaging technology has also begun to gain momentum. Stepper lithography machines are also unable to cope with this type of large-area packaging, and direct write lithography technology will be the best choice.

In the field of semiconductors, lithography technology is mainly divided into mask lithography and direct write lithography, depending on whether a mask is used. Mask lithography can be further divided into proximity/contact lithography and projection lithography.Direct-write lithography, also known as maskless lithography, refers to the process of focusing and projecting a high-precision light beam controlled by a computer onto the surface of a substrate coated with a photosensitive material, and directly performing scanning and exposure without a mask.For a long time, mask lithography was the best choice in the lithography process; but as costs continue to rise, maskless direct writing lithography may gradually attract industry attention in the future due to its cost advantages and industry layout. Especially in the field of advanced packaging, direct writing lithography is gradually becoming a key force in promoting industry innovation with its unique advantages and broad market potential.

How direct write lithography changes the advanced packaging market landscape

As the leader in the direct writing lithography equipment segment in China, Xingji Micro Equipment is accelerating its layout in substrates, advanced packaging, new display, mask plate making, power discrete devices, photovoltaic copper plating, etc., as the demand for domestic mid-to-high-end PCB and IC substrates grows and the demand for localization rate increases. Pan Changlong said that in the field of advanced packaging,In addition to the cost and easy operation advantages brought by the maskless design, the direct-write lithography equipment from Xingji Micro-Equipment has advantages in RDL, interconnection, intelligent deviation correction, and applicability to large-area chip packaging. The equipment is progressing smoothly on the client side and has received continuous repeat orders from leading advanced packaging customers in mainland China.

Pan Changlong summarized several advantages of direct writing lithography in advanced packaging. First, the production of masks is often time-consuming and costly. Direct writing lithography does not use the masks required by traditional stepping lithography.By digitally exposing patterns directly on silicon wafers, the time from product design to market is greatly shortened and manufacturing costs are significantly reduced.In addition, direct-write lithography technology can adapt to complex RDL designs and multi-layer packaging structures, which may be difficult to achieve with traditional step-by-step lithography. Customers can more flexibly adjust and optimize the design to meet different needs, especially in the R&D or sample development stages.

Secondly, direct write lithography reduces the need for mask exchange and splicing, simplifies the production process, and thus improves production efficiency. Especially with the increase in packaging area, such as the development of technologies such as CoWoS-L and FoPLP, direct write lithography can effectively meet the challenges of large-size packaging.It can handle large-area packaging designs that exceed the traditional mask size, avoid mask splicing problems, and improve production efficiency. At the same time, the direct lithography free multi-segmentation and intelligent expansion and contraction mode have excellent quality in dealing with large-size multi-layer warping deformation in board-level packaging.

Finally, in response to the current market demand for localization and reducing external dependence, the mainland is stepping up efforts to develop advanced packaging such as CoWoS and Chiplet to make up for the performance gap under the limitation of advanced processes. In this context, direct write lithography technology provides an independent and controllable solution, which helps reduce supply chain risks and enhance the competitiveness of domestic industries.

"As the requirements for high-performance and high-computing chips continue to increase, the demand for advanced packaging technologies such as CoWoS-L and FoPLP will continue to grow. With the emergence of future products such as large-size RDL and SOW, direct write lithography technology will usher in a broad market space with its advantages in large-size packaging and cost." Pan Changlong said.At present, the line width of Xingji Micro-Equipment Equipment has been as low as 2um, and the processes involved include vertical wiring TSV, horizontal wiring Bumping RDL, etc., meeting the requirements of advanced packaging customers with flexible digital masks and high yield. Currently, many devices have been delivered to clients, and the stability and functionality of the product have been verified.

It is worth noting that in addition to the photolithography process, direct write lithography also demonstrates significant technical advantages in the fields of wafer cutting and intelligent deviation correction.

Pan Changlong pointed out that in the chip manufacturing process, a cutting process is needed to slice the wafer. However, traditional diamond cutting, grinding wheel cutting or laser cutting will cause serious damage to the wafer, leading to problems such as wafer stress, fragmentation, and chip performance degradation. At present, in the field of advanced packaging, high-end customers have begun to use plasma cutting of deep silicon etching (DRIE) process to replace traditional cutting methods. However, DRIE requires an exposure process, but this exposure process is not complicated. Direct write lithography technology can directly draw precise cutting paths on silicon wafers or other substrate materials. These patterns can be simple straight lines, curves or other complex geometric shapes, and can achieve smoother and more precise cutting edges, reducing stress and damage that may be introduced by traditional cutting methods such as knife cutting or laser cutting. In addition, since direct write lithography uses digital beams and virtual masks, it does not need to make and replace physical masks for each different cutting pattern, which greatly saves cost and time.

Another typical CoWoS scenario is the integration of multiple HBMs in AI chips, which requires stacking multiple DRAM chips to form a large-capacity storage unit. Direct write lithography technology can be used to accurately draw cutting paths in this process to facilitate chip cutting and stacking.Compared with traditional cutting methods, it not only improves the cutting accuracy, but also helps to achieve tighter chip stacking, thereby improving storage density and performance.In addition, direct write lithography technology can also ensure that the surface of the chip after cutting is highly flat, which is crucial for subsequent processes such as hybrid bonding.

"The application of direct-write lithography in these two cutting scenarios can not only improve the precision and quality of cutting, but also reduce production costs and time, and improve overall production efficiency." Pan Changlong emphasized, "Through direct-write lithography, more flexible design adjustments and faster product iterations can be achieved to meet the market demand for high-performance, high-density chips."

In addition, direct-write lithography technology is increasingly used for intelligent deviation correction.

Pan Changlong explained that there are three major technical difficulties in the wafer reconstruction packaging of advanced packaging. The first is die shift, which refers to the deviation of the actual die position and the preset position due to the offset, expansion and contraction during the chip transfer process, which requires correction; the second is warpage, which is a deformation caused by the mismatch of the thermal expansion coefficients of the EMC material and the silicon wafer, which will lead to poor exposure; the third is residual glue. For the problem of die offset, direct write lithography can correct the pattern of the wiring or PI layer or bump correction to ensure the accuracy of the RDL layer pattern. In addition, in the FoWLP chip placement process, the PI correction scheme based on direct write lithography can well reduce the chip placement error of the chip placement machine. Therefore, in the fields of die offset, substrate warpage, substrate deformation, etc., the adaptive adjustment capability of direct write lithography technology gives it the advantages of high yield and good consistency.

Compared with stepper lithography, direct-write lithography has the advantages of achieving real-time pattern adjustment without a physical mask, improving production efficiency and yield, and is therefore able to meet the complex deflection correction requirements of multi-layer and large-size packaging. Its flexibility and high-precision deflection correction capability simplify the production process, reduce costs, and support the rapid development of advanced packaging technology to meet the market's demand for high-performance, high-density chips.

Opportunities and challenges coexist, and the direct writing lithography ecosystem is being reshaped

According to the estimates of Yole and Jiwei Consulting, the global advanced packaging market size will grow from US$37.9 billion to US$48.2 billion from 2022 to 2026, with a CAGR of 6.2%. In the future, the proportion of advanced packaging technology in the entire packaging market is gradually increasing, and the development of 3D packaging, fan-out packaging (FOWLP/PLP), fine-pitch wire bonding technology, and system-level packaging (SiP) technologies have become important ways to continue Moore's Law.

At the same time, Yole also predicts that in the field of IC advanced packaging, laser direct writing lithography equipment will gradually mature and occupy a certain market share in the next three years, with good market application prospects. It is true that direct writing lithography technology has begun to emerge in the field of advanced packaging, but it still needs to overcome a series of technical and market challenges before it can be used in large-scale mass production.

Pan Changlong pointed out that, first of all,With the development of advanced packaging technology, the requirements for lithography accuracy are getting higher and higherDirect-write lithography technology needs to further improve its resolution to meet the requirements of smaller line width and higher density packaging.Secondly, direct-write lithography cannot yet fully compete with stepper lithography in terms of yield and production speed (UPH). The bottleneck of yield mainly lies in the fact that there is still no photoresist and supporting light source specially developed for direct-write lithography on the market.Traditional photoresist and dielectric layer materials are designed for stepper lithography machines, and direct-write lithography technology needs to be better matched with these materials to ensure lithography quality and efficiency.Finally, many packaging customers still lack understanding of direct write lithography technology, and more market education and technology popularization are needed to increase customer awareness and acceptance.How to highlight the unique advantages of Xingji Micro-Equipment in the market competition and win the trust of customers is also a big challenge.

As the development of the domestic semiconductor industry in the field of advanced processes is limited, the demand for advanced packaging is increasing day by day. At present, the research and development of 2.5D and 3D packaging fields such as CoWoS in the mainland is accelerating. In promoting the localization of advanced packaging, Xingji Micro-Equipment has formulated and adopted a series of practical and effective plans and measures.

"Localized R&D is one of the core strategies of Xingji Micro-Equipment. The company has established a strong local R&D team, focusing on technological innovation and product development to ensure that the technology can respond to the needs of domestic customers in a timely manner.Through localized R&D, Xingji Micro-Equipment can quickly adapt to market changes and promote technological progress. "Pan Changlong said, "In terms of improving the yield rate and production efficiency of direct writing lithography, Xingji Micro-Equipment has also established close cooperation with domestic upstream and downstream industrial chains. For example, in terms of supporting photoresists, Xingji Micro-Equipment is working closely with Japanese and mainland i-line and KrF photoresist manufacturers to conduct production verification and formula adjustment to improve the feasibility of mass production. At the same time, Xingji Micro-Equipment has also established close cooperative relationships with domestic packaging factories, design companies and wafer fabs to understand customer needs and usage feedback and provide them with customized solutions. "

It is worth mentioning that,Xingji Micro Equipment is committed to increasing the proportion of localized parts and components. Currently, more than 90% of the parts and components have been localized.This not only reduces dependence on imported parts and enhances the stability of the supply chain, but also reduces production costs and improves the market competitiveness of products.

As the technology continues to mature and the market gradually recognizes it, the entire ecological chain will be reshaped. All links in the ecological chain, from material suppliers to equipment manufacturers, and finally packaging companies, have begun to actively adapt to this change and explore new products, new processes and new solutions that are compatible with direct write lithography technology. This cross-industry and cross-field cooperation will further accelerate the innovation and application of direct write lithography technology.

It is believed that direct write lithography will not only play an increasingly important role in the field of advanced packaging, but will also become an important driving force for reshaping the domestic semiconductor industry chain structure and enhancing industrial competitiveness.