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"science and technology innovation board daily" september 3rd according to korean media theelec, samsung is testing the gas cluster beam (gcb) equipment provided by tokyo electron (tel) in order to improve its extreme ultraviolet (euv) lithography process. tokyo electron confirmed that the company is evaluating the performance of the equipment with its customers to decide whether to use it in wafer foundries.

public information shows that tokyo electron is a major supplier of semiconductor manufacturing equipment, specializing in semiconductor etching, deposition and cleaning. its customers include advanced logic and memory chip manufacturers such as tsmc, intel, samsung, etc.

the device included in the test evaluation is called acrevia, which was launched in july this year. it uses a directional gas cluster beam to etch at the optimal wafer tilt angle, thereby achieving precise adjustment of the critical size and shape of the euv lithography pattern.

this not only improves the accuracy of the lithography pattern, but also significantly reduces the risk of damage to the wafer surface. tokyo electron said that as a pattern shaping tool, the device can improve the pattern edge roughness and reduce random lithography defects, thereby improving the yield.

samsung expects thatuse of gcb equipment will help reduce costs at advanced nodesin fact, once the gcb equipment improves the wafer yield, it can reduce the number of ineffective uses of lithography equipment, thereby helping to extend the service life of the equipment. samsung also emphasized that this will reduce random errors in the pattern processing process of euv lithography technology. fewer errors means lower costs.

in recent years, with the continuous development of process technology, euv lithography equipment has become a must-have for all wafer foundry manufacturers, and high costs have also come with it. in may this year, tsmc senior vice president zhang xiaoqiang complained when commenting on asml's latest high numerical aperture extreme ultraviolet lithography machine at a technical seminar: "the price is too high."

to make matters worse, in order to continue to shrink chip design, chip manufacturers often use multi-patterning lithography technology, which splits a complex single-layer pattern into multiple simple patterns and performs multiple exposures and etchings on different masks to achieve the final desired pattern.

problems arise. although the large-scale application of multiple patterning has reduced the size of the design, it has also introduced risks of technical defects such as alignment problems and stacking errors. in addition, multiple patterning requires multiple exposure and etching cycles, which greatly expands the manufacturing process. each additional exposure also requires additional masks and more lithography tools. in a nutshell,chip yield and production capacity are getting lower and lower, and costs are further increasing.。

against this backdrop, semiconductor equipment manufacturers have launched a wave of cost reduction and efficiency improvement. in addition to tokyo electron's acrevia gcb equipment, applied materials launched the centura sculpta system with similar functions in february last year and supplied it to intel.

it was reported at the time that the system could save chip manufacturers the following costs: 1) approximately $250 million in capital costs when producing 100,000 wafers per month; 2) $50 in manufacturing costs per wafer; and 3) more than 15 kilowatt-hours of energy per wafer.

in addition, in february this year, applied materials also launched a new electron beam measurement equipment specifically designed to accurately measure the critical dimensions of semiconductor devices using euv and emerging high-na euv lithography technologies.

regarding the tokyo electron gcb equipment entering the test evaluation, korean media commented: "the euv patterning market is dominated by applied materials, and tokyo electron's new equipment poses a challenge to it."