news

한어Русский языкEnglishFrançaisIndonesianSanskrit日本語DeutschPortuguêsΕλληνικάespañolItalianoSuomalainenLatina

Machine Heart Report

Editor: Zenan, Xiaozhou

Millions of connections are made on one square millimeter of silicon.

From nanometers to angstroms, chipmakers are working hard to shrink the size of their circuits. But a technology involving even larger dimensions — hundreds or thousands of nanometers — could be just as important in the next five years to meeting our growing demand for computing power.

The technology, called direct hybrid bonding, can stack two or more chips together in the same package to build so-called 3D chips. Although the pace of transistor shrinkage is slowing as Moore's Law breaks down, chipmakers can still increase the number of transistors in processors and memory in other ways.

In May, at the IEEE Electron Components and Technology Conference (ECTC) in Denver, research teams from around the world unveiled various hard-won improvements to the technology, including some results showing that the density of connections between 3D stacked chips could reach a record level: about 7 million connections per square millimeter of silicon.

All of these connections are necessary because of new advances in semiconductor technology, Intel's Yi Shi reported at ECTC. Moore's Law is now governed by a concept called system technology co-optimization (STCO), where the functions of a chip, such as cache, input/output, and logic, are manufactured separately using state-of-the-art process technologies. These subsystems can then be assembled using hybrid bonding and other advanced packaging techniques so that they act like a single piece of silicon. But this is only possible if there are high-density connections that can carry data between separate pieces of silicon with little latency or energy consumption.

Among all advanced packaging technologies, hybrid bonding provides the highest density of vertical connections. As a result, it is the fastest growing area in the advanced packaging industry, and Gabriella Pereira, technology and market analyst at Yole Group, said that by 2029, the market size of this direction will more than double to $38 billion. By then, hybrid bonding is expected to account for about half of the market.

In hybrid bonding, copper pads are built on the top surface of each chip. The copper is surrounded by an insulating layer (usually silicon oxide), and the pads themselves are slightly recessed into the surface of the insulating layer. After chemically modifying the oxide, the two chips are pressed together face to face, aligning each recessed pad. The sandwich is then slowly heated, causing the copper to expand into the gap and fuse, thus connecting the two chips.

1. Hybrid bonding starts with two wafers or a chip and a wafer facing each other. The mating surface is covered with an oxide insulating layer and a slightly recessed copper pad, which is connected to the interconnect layer of the chip.

2. Press the wafers together to form an initial bond between the oxides.

3. The stacked wafers are then slowly heated to firmly connect the oxides and expand the copper to form an electrical connection.

a. To form a stronger bond, engineers need to flatten the last few nanometers of the oxide. Even a slight bump or warp can destroy a dense connection.

b. The copper must be recessed from the oxide surface to just the right degree. Too much and no connection can be made, too little and the wafer will be pushed away. Researchers are working on how to control the copper down to the level of a single atomic layer.

c. The initial connection between the wafers is a weak hydrogen bond. After annealing, the connection becomes a strong covalent bond. The researchers expect that using a different type of surface, such as silicon carbonitride, will have more locations where chemical bonds can form, which will make the connection between the wafers stronger.

d. The final step of hybrid bonding can take hours and requires high temperatures. The researchers hope to reduce the temperature and shorten the process time.

e. Although the copper on two wafers is pressed together to form an electrical connection, the grain boundaries of the metal usually do not cross from one side to the other. Researchers are trying to form large single-crystalline copper grains on the boundaries to improve conductivity and stability.

Hybrid bonding can either connect a single die of one size to a wafer full of larger-sized chips, or it can bond two full wafers of the same size together. The latter process is more mature than the former, of course, in part because of its use in camera chips. For example, engineers at European microelectronics research institute Imec have created some of the densest wafer-to-wafer bonds ever made, with a bond distance (or pitch) of just 400 nanometers. But Imec has only achieved a chip-to-wafer bonding pitch of 2 microns.

That’s a big improvement over the advanced 3D chips in production today, which have connections about 9 microns apart. And it’s an even bigger leap over the previous generation of technology: “microbumps” of solder, which have connections a few tens of microns apart.

“Once the equipment is available, it’s easier to align wafer to wafer than chip to wafer. Most microelectronics processes are done on whole wafers,” said Jean-Charles Souriau, head of integration and packaging science at French research institute CEA Leti. But chip-to-wafer (or die-to-wafer) technology could shine in high-end processors, such as those from AMD, which use the new technology to assemble the computing cores and caches in its advanced CPUs and AI accelerators.

To push the pitch ever tighter in both cases, researchers are focusing on making the surface flatter, allowing the bound wafers to adhere better together and reducing the time and complexity of the entire process. Getting this right could revolutionize the way chips are designed.

WoW, reduce spacing

The tightest pitches achieved in recent wafer-on-wafer (WoW) research — about 360nm to 500nm — have come with a lot of effort on one thing: flatness. To bond two wafers together with 100nm precision, the entire wafer must be almost perfectly flat. If it's slightly warped or twisted, the entire part won't connect.

The planarization of wafers requires a process called chemical mechanical planarization (CMP). It is critical to chip manufacturing, especially for producing the interconnect layers above the transistors.

“CMP is the key parameter for hybrid bonding that we have to control,” said Souriau. The results presented at ECTC showed CMP taken to another level, not only flattening the entire wafer but also reducing the roundness of the insulating layer between the copper pads to the nanometer level to ensure better connections.

Other researchers are working to ensure that these flat parts can be bonded together strongly enough. They’ve tried using different surface materials, such as silicon carbonitride instead of silicon oxide, and using different schemes to chemically activate the surfaces. Initially, when the wafers or chips are pressed together, they’re held together by relatively weak hydrogen bonds, and the concern is whether they’ll stay in place during further processing steps. After being joined, the wafers and chips are slowly heated, a process called annealing that’s designed to form stronger chemical bonds. Just how strong those bonds are — or even how to figure them out — was the subject of much of the research presented at ECTC.

The ultimate bond strength comes in part from the copper connection. An annealing step causes the copper to expand across the gap, forming a conductive bridge. Controlling the size of the gap is key, explains Samsung’s Seung Ho Hahn. Too little expansion and the copper won’t fuse, too much and the wafer will be pushed apart. This is a nanoscale problem, and Hahn reports on research into a new chemical process that he hopes will accomplish this by etching away the copper one atomic layer at a time.

The quality of the connection matters, too. The metal in a chip’s interconnects isn’t a single crystal; it’s made up of many grains, oriented in different directions. Even after the copper expands, the metal’s grain boundaries typically don’t cross from one side to the other. That crossing should lower the connection’s resistance and improve its reliability. Researchers at Tohoku University in Japan report a new metallurgical scheme that could eventually produce large single crystals of copper that span the boundaries. “This is a huge change,” says Takafumi Fukushima, an associate professor at Tohoku. “We’re now analyzing the reasons behind it.”

Other experiments discussed at ECTC focused on streamlining the bonding process. Some have tried to lower the annealing temperature needed to form the bonds, typically around 300 °C, to minimize the risk of damage to the chip from prolonged heating. Applied Materials researchers described advances in a method that could drastically reduce the time needed for annealing—from hours to just 5 minutes.

Excellent CoW

Imec uses plasma etching to cut the chips and give them chamfered corners. The technique eliminates mechanical stress that could interfere with bonding.

Currently, chip-on-wafer (CoW) hybrid bonding is more useful for advanced CPU and GPU manufacturers: it allows chipmakers to stack small chips of different sizes and test each one before bonding it to another to ensure they don’t have problems. After all, one defective part can doom the entire expensive CPU.

But CoW has all the difficulties of WoW, with fewer options to mitigate them. For example, CMP is designed to flatten wafers, not individual die. Once a die is cut from the source wafer and tested, fewer steps can be taken to improve its bond readiness.

Nonetheless, Intel researchers have reported CoW hybrid bonding with 3 μm pitch, and as mentioned above, a team at Imec has succeeded in achieving 2 μm pitch, primarily by making the transferred dies very flat while they are still attached to the wafer and keeping them clean throughout the process.

Both teams used plasma etching to cut the chips, rather than the commonly used saw blade method. Unlike sawing, plasma etching does not cause edge chipping, which can create debris that could interfere with connections. It also allows the Imec team to shape the chips, creating chamfered corners to relieve mechanical stress that could damage connections.

Several researchers at ECTC said CoW hybrid bonding is critical to the future of high-bandwidth memory (HBM). HBM is a stack of DRAM dies (currently 8-12 dies high) on top of a control logic chip. HBM is often placed in the same package as a high-end GPU and is critical for processing the massive amounts of data required to run large language models such as ChatGPT. Today, HBM dies are stacked using microbump technology, so there are tiny solder balls surrounded by organic filler between each layer.

But as AI drives up memory demands further, DRAM makers want to stack 20 or more layers in HBM chips. The volume taken up by the microbumps means these stacks will quickly become too tall to fit properly in GPU packages. Hybrid bonding would shrink the height of the HBM and make it easier to remove excess heat from the package because there would be less thermal resistance between the layers.

At ECTC, Samsung engineers demonstrated that hybrid bonding can produce a 16-layer HBM stack. “I think it’s possible to make 20-layer or more stacks using this technology,” said Samsung senior engineer Hyeonmin Lee. Other new CoW technologies are also helping to bring hybrid bonding to high-bandwidth memory.

Souriau said CEA Leti researchers are exploring so-called self-alignment techniques. This will help ensure good CoW connections using only chemical processes. Some parts of each surface will be made hydrophobic, while other parts will be made hydrophilic, causing the surface to automatically slide into place.

At ECTC, researchers from Tohoku University and Yamaha Robotics reported work on a similar scheme, using the surface tension of water to align 5-μm pads on an experimental DRAM chip with better than 50-nm accuracy.

Upper limit of hybrid bonding

Researchers will almost certainly continue to reduce the pitch of hybrid bonding connections. “A 200nm WoW pitch is not only possible, it’s ideal,” said Han-Jong Chia, program manager for pathfinding systems at TSMC. TSMC plans to introduce a technology called backside power delivery within two years. Intel plans to do the same by the end of this year. This technology places a chip’s power-delivery interconnects below the silicon surface rather than above it.

TSMC researchers calculated that by eliminating these power conduits, the top layers can better connect to smaller hybrid bond pads. Backside power delivery using 200 nm bond pads will reduce the capacitance of 3D connections so much that energy efficiency and signal speed measurements will be eight times better than what can be achieved using 400 nm bond pads.

Chip-on-wafer hybrid bonding is more useful than wafer-on-wafer bonding because it can place a die of one size onto a wafer of larger die. However, the achievable connection density is lower than with wafer-on-wafer bonding.

At some point in the future, if the bond pitch shrinks further, it might become practical to “fold” circuit blocks, Chia said. Some of the now-long connections within a block might be able to take vertical shortcuts, speeding up computations and reducing power consumption.

And hybrid bonding may not be limited to silicon. “Today, there is a lot of progress with silicon-to-silicon wafers, but we are also looking at hybrid bonding of gallium nitride to silicon wafers and glass wafers… Everything is possible,” said CEA Leti’s Souriau. They have even proposed hybrid bonding for quantum computing chips, which would involve aligning and bonding superconducting niobium instead of copper.

Reference: https://spectrum.ieee.org/hybrid-bonding Return to Sohu to see more