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tsmc is gearing up to meet the production capacity demand for advanced packaging of ai servers.

at the july earnings conference, tsmc chairman wei zhejia also responded to analysts' questions about the tight production capacity of cowos for advanced packaging. he mentioned that the popularity of artificial intelligence has driven the demand for cowos. tsmc's cowos demand is very strong. tsmc continues to expand and hopes to achieve supply and demand balance in 2025-2026. the capital expenditure of cowos cannot be clearly stated at present because it is being worked hard to increase it every year. it was mentioned last time that this year's production capacity has more than doubled, and the company is also working very hard to expand its production capacity.

in order to achieve this goal, tsmc packaging is expanding production rapidly.

tsmc continues to expand production by buying and building factories

in terms of tsmc's packaging expansion, the earlier acquisition of innolux's 4th plant in nankai, code-named ap8, will be a wise choice for the company's packaging development. because through this transaction, the environmental assessment stage, which takes years, will be omitted, and the company expects to put the plant into production in the second half of next year. according to taiwanese media, the plant's future production capacity is 9 times larger than that of the zhunan advanced packaging plant, and it will include wafer foundry and 3d ic.

in mid-august this year, tsmc announced that it would spend nt$17.14 billion to purchase innolux's 5.5-generation lcd panel factory in southern taiwan science park. the factory was originally favored by memory giant micron, but it was not until tsmc and innolux announced the factory transaction information that the outside world realized that tsmc had taken the lead.

the supply chain revealed that the main reason why tsmc purchased innolux's 4th plant in southern taiwan science park is to save the environmental impact assessment process that takes years. unlike the advanced packaging plant in chiayi, it only needs to carry out factory modification projects and can start production within less than a year after the machines are moved in.

equipment-side industry players pointed out that after the factory transaction was finalized, tsmc started the plant construction plan for the ap8 plant, with the goal of starting production in the second half of 2025. related machine equipment manufacturing orders are being carried out simultaneously, and it is expected that the machines will be delivered in april next year. with about one quarter of trial production, it will not be difficult to start production in the second half of the year.

since the scale of the ap8 plant is 9 times larger than that of the zhunan advanced packaging plant, the supply chain believes that it will not only have cowos production capacity for advanced packaging, but also that advanced process wafer foundry, fan-out packaging, and 3d ic production lines may be stationed in the future.

in addition to purchasing the factory, tsmc's previous factory construction is also progressing steadily.

in may this year, tsmc's cowos advanced packaging plant in chiayi science park was under construction, but during the construction process, suspected ruins were dug up and are now being handled in accordance with the cultural heritage act. the outside world is concerned about the progress of the plant. however, taiwan said that it expects the relevant cleanup work under the cultural heritage act to be completed in october this year, and tsmc's chiayi advanced packaging plant's planned installation in the third quarter of next year will not be affected.

according to previous plans, tsmc will set up two cowos advanced packaging plants in chiayi, and originally planned to start mass production in 2028. in terms of technology, it is reported that this plant will mainly focus on system integrated single chip (soic). tsmc is also optimistic about 3d packaging. its current customers include chip giant amd mi300, and the number of customers is expected to increase further by 2026.

due to the strong demand for cowos, tsmc is still looking for suitable locations for factory expansion throughout taiwan. the tongluo plant planned earlier encountered water and soil problems, and the first plant in chiayi was temporarily blocked (the site was dug up). focusing on the long-term huge demand, tsmc needs to seek more matching locations in advance. according to previous media reports, yunlin county magistrate zhang lishan pointed out that the county government has independently launched the "huwei industrial park plan" and is trying its best to attract tsmc to set up a factory in the area of ​​about 29.75 hectares, which is adjacent to the central science park huwei park.

but recently there are reports that, in addition to the land around the nanke area that tsmc recently purchased, tsmc has decided to move its factory site from yunlin to pingtung. tsmc said that there are many considerations in choosing the location of the factory and no possibility is ruled out. at the beginning of this year, there was even news that tsmc, the leading wafer foundry, was considering building an advanced packaging plant in japan, which is enough to show the popularity of this packaging technology.

american legal persons estimate that tsmc's monthly cowos production capacity may exceed 32,000 pieces by the end of the year. if cooperative manufacturers are included, the monthly production capacity will have the opportunity to approach 40,000 pieces. by the end of 2025, the monthly production capacity will be around 70,000 pieces.

tsmc vice president of operations, advanced packaging technology and services he jun also revealed at the semiconductor expo that the cowos advanced packaging production capacity is expected to achieve an annual compound growth rate of more than 50% from 2022 to 2026, and will continue to expand production until 2026. in the past, it took 3 to 5 years to build a factory, but now it has been shortened to 2 years to meet customer needs.

in the "ai chip special report" published by digitimes research center in mid-august, it was pointed out that the growth momentum of advanced packaging is stronger than that of advanced processes. in the field of advanced packaging, ai chips are highly dependent on tsmc's cowos packaging technology. therefore, tsmc's cowos capacity expansion cagr from 2023 to 2028 will exceed 50%, and the average annual compound growth rate of the wafer foundry industry's advanced process expansion below 5nm from 2023 to 2028 will reach 23%.

while significantly increasing its production capacity, tsmc is also iterating the company's packaging technology in order to provide more support to its customers.

continuous upgrade of packaging technology

at a recent seminar for north american customers, the chipmaker unveiled an ambitious roadmap for chip packaging and cutting-edge optical interconnect technologies, advances that could unleash a wave of computing performance in the coming years.

first up is chip packaging technology, which tsmc has dubbed “cowos” (chip on wafer substrate), which is essentially an enhanced version of the typical chiplet design, where multiple smaller chips are integrated into a single package. but tsmc is taking it to new levels of incredible scale and complexity.

the current iteration of cowos supports interposers (silicon substrates) up to 3.3 times the size of a typical photomask used in lithography. but by 2026, tsmc’s “cowos_l” will increase that to about 5.5 times the mask size, leaving room for larger logic chips and up to 12 hbm memory stacks. and just a year later in 2027, cowos will expand to an eye-popping 8x mask size or even larger.

we’re talking about an integrated package that measures 6,864 square millimeters, much larger than a credit card. these cowos behemoths can integrate four stacked logic chips along with a dozen hbm4 memory stacks and additional i/o chips.

to give you an idea of ​​the scale, broadcom also showed off a custom ai processor with two logic chips and 12 memory stacks. the chip looked bigger than nvidia’s latest powerful accelerator. the chip, which uses taichidan chip-on-wafer-substrate (cowos) packaging technology, has a computing chip that is close to the limit of the mask (858 square millimeters, 26 mm x 33 mm).

but this chip is still tiny compared to the chips tsmc has in store for 2027. because, as mentioned above, tsmc expects its solution to use substrates up to 120x120 mm.

in tsmc's packaging landscape, 3d ic will undoubtedly play an important role.

also at this year's technology symposium, tsmc outlined a roadmap that would shrink the technology from the current 9μm bump pitch all the way down to a 3μm pitch by 2027, stacking a combination of a16 and n2 chips together.

according to reports, tsmc's 3d stacked integrated chip system (soic) technology is tsmc's implementation of hybrid wafer bonding. hybrid bonding allows two advanced logic devices to be stacked directly together, enabling ultra-dense (and ultra-short) connections between the two chips, mainly for high-performance components. currently, soic-x (bump-free) is used for specific applications, such as amd's cpu 3d v cache technology, and their instinct mi300 series ai products. although the adoption rate is growing, the current generation of technology is limited by chip size and interconnect spacing.

but if all goes according to tsmc’s plan, those limitations are expected to disappear soon. soic-x technology will advance rapidly, and by 2027 it will be possible to assemble a chip that pairs a reticle-sized top die made on tsmc’s cutting-edge a16 (1.6nm) with a bottom die produced using tsmc’s n2 (2nm). the chips will in turn be connected using 3μm bonding pitch through-silicon vias (tsvs), three times the density of today’s 9μm pitch. such small interconnects will allow for a much greater number of connections overall, greatly increasing the bandwidth density (and therefore performance) of the assembled chip.

in addition to developing bumpless soic-x packaging technology for devices that require extremely high performance, tsmc will also launch a bumped soic-p packaging process in the near future. soic-p is designed for cheaper, lower-performance applications that still require 3d stacking but do not need the additional performance and complexity that bumpless copper-to-copper tsv connections bring. this packaging technology will enable a wider range of companies to take advantage of soic, and while tsmc cannot speak for its customers' plans, a cheaper version of the technology may make it suitable for more cost-conscious consumer applications.

according to tsmc's current plan, by 2025, the company will offer front-to-back (f2b) bump soic-p technology, which can mate a 0.2 mask size n3 (3nm) top chip with an n4 (4nm) bottom chip and connect it using 25μm pitch microbumps. in 2027, tsmc will launch front-to-back (f2f) bump soic-p technology, which can place an n2 top chip on an n3 bottom chip with a pitch of 16μm.

there is still a lot of work to be done to make soic more popular and accessible among chip developers, including continued improvements to its chip-to-chip interface. but tsmc seems very optimistic about industry adoption of soic, predicting that about 30 soic designs will be released by 2026-2027.

according to a report by taiwan media trendforce, citing a speech by tsmc's vice president of advanced packaging technology and services, he jun, at an earlier semicon taiwan event, tsmc believes that 3d ic is a key method for integrating ai chip memory and logic chips. he jun also pointed out that the global semiconductor market is expected to become a trillion-dollar industry in 2030, with hpc and ai as key drivers, accounting for 40%, which also makes ai chips a key driver of 3d ic packaging.

he jun said that the reason why customers choose to use 3d ic platforms for multi-chip design and manufacturing of ai chips is related to its lower cost and reduced design conversion burden.

he jun explained that by converting the traditional soc+hbm design to chiplet and hbm architecture, the new logic chip will be the only component that needs to be designed from scratch, while other components such as i/o and soc can use existing process technology. this approach can reduce mass production costs by up to 76%. he pointed out that although the new architecture may increase production costs by 2%, the total cost of ownership (tco) is improved by 22% due to these efficiency improvements.

however, 3d ic still faces challenges, especially in improving differential performance. he jun emphasized that the key to improving 3d ic production capacity lies in chip size and process complexity. as for chip size, larger chips can accommodate more chips, thereby improving performance. however, this also increases the complexity of the process, and the difficulty may increase by three times. in addition, there are risks related to chip misalignment, breakage, and failures during extraction.

to address these risk challenges, he jun identified three key factors: tool automation and standardization, process control and quality, and support from the 3dfabric manufacturing platform.

for tool automation and standardization, the differentiated capabilities of tsmc and its tool suppliers are crucial. currently, tsmc has 64 suppliers and has the ability to take the lead in the field of advanced packaging tools. in terms of process control and quality, tsmc uses high-resolution pnp tools and ai-driven quality control to ensure comprehensive and robust quality management, and finally integrates 1,500 materials in the supply chain with the 3dfabric manufacturing platform for optimization.

optoelectronic packaging, tsmc's next goal

while vigorously developing traditional electrical packaging, light has also become a focus of tsmc.

at this year's technical seminar, tsmc also revealed its "3d optical engine" strategy, which aims to integrate lightning-fast optical interconnects into its customer designs. as bandwidth demands surge, copper wires simply cannot meet the needs of cutting-edge data centers and hpc workloads. optical links that utilize integrated silicon photonics can provide higher throughput and lower power consumption.

tsmc said it is developing compact universal photonic engine (coup) technology to support the explosive growth in data transmission brought about by the ai ​​boom. coupe uses soic-x chip stacking technology to stack electronic chips on top of photonic chips, providing the lowest impedance at the chip-to-chip interface and higher energy efficiency than traditional stacking methods. tsmc plans to certify coupe as a small pluggable device in 2025, and then integrate it into the cowos package as a co-packaged optical device (cpo) in 2026, introducing optical connections directly into the package.

tsmc packages electronic and photonic devices together using advanced 3d stacking technology. the first generation plugs into a standard fiber port at 1.6 tbps, twice the current high-end ethernet. the second generation increases the speed to 6.4 tbps by integrating the coupe with the processor into tsmc's cowos package. the final result of the roadmap is the cowos "coupe intermediate layer" design, which has an amazing fiber bandwidth of 12.8 tbps.

regarding tsmc's silicon photonics technology, although the company has only recently announced its plan, according to taiwanese media reports, they actually had plans for it a long time ago.

taiwanese media said that by using the incopat patent database to search for the current status of patent technology for cpo co-packaging optics, it was found that tsmc has already started to deploy in this technical field and is currently one of the main patent holders in this field. for example, as early as 2013, tsmc proposed the us9423578b2 patent, proposing to use optical signals instead of electrical signals for data transmission to solve the problem that electrical signals used in various types of ics are also affected by the increased delay caused by the capacitance, inductance or resistance in the ic. since this technology was proposed earlier, it has also become a precedent for many other patents.

earlier this month, tsmc also participated in the establishment of a silicon photonics alliance, laying a solid foundation for the popularization of this technology.

in his speech at the founding of the alliance, tsmc vice president xu guojin mentioned that the entire semiconductor industry has gone through 60 or 70 years of development, from different component designs, gradually focusing on the development and application of cmos (complementary metal oxide semiconductor) component technology, which is also the process technology used by silicon photonics to integrate photons and electronics. he pointed out that when cmos became the mainstream of commercial applications, the industry development, whether in product design and development, the division of labor between upstream and downstream was clearer, especially energy saving was a great advantage.

xu guojin believes that currently optical components and silicon photonic components are still in the early stages of flourishing. with the huge demand for massive computing and data transmission required in the ai ​​era, energy consumption has become an important issue, and the introduction of silicon photonic components has become an important trend in data centers.

from the above reports, we can also see that this front-end giant has become a well-deserved giant in the packaging field.

reference links

https://www.bnext.com.tw/article/80382/semi-silicon-photonics-industry-alliance-launch

https://www.anandtech.com/show/21414/tsmcs-3d-stacked-soic-packaging-making-quick-progress-3um-pitch-in-2027

https://synergytek.com.tw/blog/2024/06/25/tsmc_cpo_technology_roadmap/

https://www.trendforce.com/news/2024/09/05/news-tsmc-to-provide-3dic-integration-for-ai-chips-in-2027-featuring-12-hbm4-and-chiplets-manufactured-with-a16/

https://www.techspot.com/news/102779-tsmc-lays-out-roadmap-massive-kilowatt-class-chip.html

https://www.anandtech.com/show/21373/tsmc-adds-silicon-photonics-coupe-roadmap-128tbps-on-package