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foreign hardware expert nemez used the "bullshit" base map of bilibili netizens to conduct a detailed analysis of the internal structural layout of lunar lake, the core ultra 200v series processor. the distribution of large and small cores is very interesting.

the core ultra 200v processor is divided into a computing module and a platform controller module, which adopt tsmc's 3nm and 6nm processes respectively, and are jointly placed on a substrate manufactured by tsmc's 22nm.

the calculation module area is 16.27×8.58＝139.60 square millimeters, the platform controller module area is 11.51×3.97＝45.69 square millimeters, the base area is 16.77×13.10=219.69 square millimeters.

compute module

platform controller module

base

another major feature of it is that it packs two lpddr5x memories, which helps save the motherboard area and notebook space, making it thinner and lighter or putting in a larger battery. it also helps improve system communication performance, reduce latency, and greatly improves system communication performance. reduce overall power consumption.

it can be seen from the analysis chart thatfour p-cores of the lion cove architecture are located on the right edge of the computing module, with a shared 12mb level 3 cache sandwiched in between, divided into four blocks of 3mb each.

each core has its own 2.5mb l2 cache, which is also divided into two blocks.

next to it are a group of four skymont architecture e-cores, collectively sharing a 12mb l2 cache, divided into three blocks.

in comparison,the area of ​​four e cores is slightly larger than that of one p core, which is undoubtedly quite commendable, because the area of ​​four e cores of the previous generation was approximately equal to one p core, and the ipc performance of this generation of e cores has been improved by 38% in integer and floating point. it increased by 68%, but the area did not increase significantly.

further to the left is the npu ai engine, which is divided into six groups of nce mac arrays. each group is guessed to have a 2mb cache.

on the left edge is the gpu core display, a total of eight cores of the xe2 lpg architecture, and an 8mb l2 cache divided into two blocks.

there are also media engines, display engines, 8mb slc system cache, and 128-bit lpddr5x-8533 memory controller.

the platform controller module contains pcie 4.0/5.0 controller, thunderbolt controller, usb 3.x/2.0 controller, wi-fi and bluetooth controller, etc.

the platform controller module and the computing module are connected to each other through two module bridges (tile bridge).