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Intel plans to release the next-generation Arrow Lake processor in 2024. The P-Core and E-Core will be upgraded to the new Lion Cove and Skymont architectures respectively. Arrow Lake will also be expanded to multiple sub-platforms, with "S" for desktops belonging to the Core Ultra 200 series, using the new LGA 1851 socket to replace the existing LGA 1700 socket.

Figure: Intel CEO Pat Gelsinger shows Arrow Lake wafer

Recently, some netizens revealed that Arrow Lake-S will have two chips, namely 8P+16E "B0" and 6P+8E "C0", and the core graphics card will be configured with up to 4 Xe cores.

B0 chips are mainly used in Core Ultra 9 and Core Ultra 7. The former has a maximum configuration of 8P+16E, while the latter has 8P+12E. Both provide 125W "K", 65W "non-K" and 35W "T" versions. The integrated graphics card is equipped with 4 Xe cores, and there should be an "F" model without integrated graphics. Most Core Ultra 5 chips coexist with B0 and C0 chips, with a maximum configuration of 6P+8E (4Xe). There will also be combinations of 6P+8E (3Xe), 6P+8E (0Xe) and 6P+4E (2Xe). However, the 35W "T" version does not have a 6P+8E (0Xe) configuration, and low-power products only use C0 chips.

In addition, except for Ultra 9 285K (8P+16E, 125W), Ultra 9 275 (8P+16E, 65W), Ultra 7 265K (8P+12E, 125W), Ultra 7 255 (8P+12E, 65W), Ultra 5 245K (6P+8E, 125W) and Ultra 5 240, the specific names of the remaining models have not yet been determined.

It is rumored that in Arrow Lake-S, each Skymont architecture E-Core cluster (4 cores) is equipped with 4MB (16-Way) L2 cache and 3MB L3 cache, while each Lion Cove architecture P-Core is equipped with 3MB (12-Way) L2 cache and 3MB L3 cache. In other words, the highest 8P+16E configuration will be equipped with 40MB L2 cache and 36MB L3 cache, a total of 76MB, which is about 12% more cache than Raptor Lake-S's 68MB.