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the first packaging product launched by tsmc is cowos (chip on wafer on substrate), which places logic chips and dram on a silicon interposer and then packages them on a substrate. morris chang said that tsmc's business model in the future will be to provide a full range of services to achieve the production and manufacturing of the entire chip.

in 2016, nvidia launched the first graphics chip gp100 using cowos packaging, which kicked off the first wave of artificial intelligence craze. later, the tpu 2.0 behind google alphago's victory over ke jie also used cowos packaging from tsmc.

today, cowos has become a technology that ai chips cannot avoid, and advanced packaging has also penetrated into the semiconductor industry, becoming a hot field that is no less popular than advanced processes.

but for tsmc, which launched foundry 2.0, cowos alone is obviously not enough, especially considering its limited production capacity, which cannot even meet nvidia's needs.it urgently needs to launch more and better packaging products.

when we look at the entire advanced packaging market, we will find that in addition to the 2.5d and 3d packaging that have been hotly discussed in the past year, several new technologies are mentioned more and more frequently. ai chips have brought cowos into the spotlight, and now it has brought foplp and glass substrates in advanced packaging onto the stage.

foplp

why has fan-out panel-level packaging (foplp) become so popular among manufacturers?

in 2016, tsmc began to develop fowlp (fan-out wafer-level packaging) technology called info (integrated fan-out packaging), which was used in the a10 chip of the iphone 7 series of mobile phones, squeezing samsung's foundry out of apple's supply chain. after that, the packaging and testing industry followed tsmc's footsteps and began to promote the fowlp solution, hoping to attract customers at a lower cost.

however, after a few years, there has not been much breakthrough in the technology of fowlp packaging solutions, and terminal applications are still stuck in mature process products such as pmic (power management ic), making it difficult to open the door to more customers.

at this time, foplp came onto the stage, switching from wafer level to panel level, combining the advantages of low unit cost and large-size packaging, which also attracted the attention of ai chip manufacturers.

the main difference between wafer-level packaging and panel-level packaging is that instead of reassembling the cut chips on a wafer, the former reassembles them on a larger panel. this enables manufacturers to package a large number of chips, thereby reducing the cost of the packaging process. it also improves packaging efficiency because the square substrate can be packaged with an area that is up to 7 times that of a round 12-inch wafer, that is, more chips can be placed in the same unit area.

image source: samsung

it is worth mentioning that this emerging market is growing very fast. gabriela pereira, semiconductor packaging analyst at yole group, said: "looking at the entire fan-out packaging market, fowlp is still the mainstream carrier type, while foplp is still considered a niche market. in terms of revenue, yole intelligence estimates in its fan-out packaging 2023 report that the foplp market size will be approximately us$41 million in 2022, and is expected to show a significant compound annual growth rate of 32.5% in the next five years, growing to us$221 million by 2028.

in fact, foplp adoption will grow faster than the overall fan-out market, with its market share relative to fowlp rising from 2% in 2022 to 8% in 2028. this means that foplp is poised to grow in the coming years as more panel production lines come online and higher yields lead to better cost benefits.”

the latest good news is that nvidia intends to use panel-level fan-out packaging (commonly known as foplp) for its latest blackwell chips. nvidia's cowos packaging capacity for blackwell products is tight, and there are rumors that blackwell gb200 may also start using foplp as early as next year (2025) instead of the original 2026 schedule. in addition, amd has also begun contacting related companies to prepare to adopt foplp in future ai chips.

in contrast, a number of packaging and testing companies in taiwan are accelerating the development of foplp.

powertech was the first semiconductor packaging and testing company in taiwan to invest in foplp mass production lines. it started building the world's first foplp production line at its third plant in hsinchu science park in 2016, and officially started mass production in 2019. powertech ceo hsieh yung-ta said that powertech is about two years ahead of the industry and is optimistic that in the future, heterogeneous packaging will adopt more foplp solutions in the ai ​​generation, and it is expected to bear fruit in 2026 and 2027.

innolux used the worthless 3.5-generation fab equipment to transform, and nearly 70% of the equipment can be used continuously, which is the largest panel size production line currently. innolux has been investing in the research and development of foplp for 8 years, and has not only obtained subsidies from the ministry of economic affairs' a+ plan, but also cooperated with the industrial technology research institute. it is expected to officially introduce mass production in the fourth quarter of this year, which will contribute 1 to 2 percentage points to revenue next year.

according to a survey by research firm trendforce, there are three main modes for the introduction of foplp packaging technology: 1. packaging and testing foundries convert consumer ic packaging from traditional packaging to foplp. 2. professional wafer foundries and packaging and testing foundries package ai gpus and convert the 2.5d packaging mode from wafer level to panel level. 3. panel manufacturers target applications such as power management and consumer ics.

the big manufacturers are also moving very quickly. tsmc chairman wei zhejia explained the progress of foplp layout for the first time at a recent earnings conference. tsmc has established a research and development team and production line.it is still in its infancy, but he expects the technology to be mature in three years, by which time tsmc will have the capacity for mass production.

immediately afterwards, at the legal briefing of ase technology holding, chief operating officer wu tianyu stated that ase has been researching panel-level solutions for more than five years, starting with 300mm×300mm, and will expand to 600mm×600mm in size in the future.

outside of taiwan, south korea's samsung is also vigorously promoting foplp packaging technology.

as early as eight years ago, samsung electro-mechanics developed foplp technology for the galaxy watch and began mass production in 2018. in 2019, samsung electronics acquired the plp business from samsung electro-mechanics for 785 billion won (about us$581 million). as of now, the galaxy watch 6 chip still uses this technology, using foplp combined with package stacking (pop) technology to integrate the cpu, pmic and dram into the chipset.

kyung-hyun kyung, former head of samsung electronics’ semiconductor (ds) division, explained the need for plp technology at the company’s shareholders meeting in march. “ai chip substrates are usually 600 mm x 600 mm or 800 mm x 800 mm in size, which requires technologies such as plp,” he said, adding, “samsung electronics is also developing and working with customers.”

samsung currently offers foplp for applications that require low-power memory integration, such as mobile and wearable devices, and it also plans to expand its 2.5d packaging technology i-cube to plp.

compared with tsmc and samsung, intel seems less enthusiastic about foplp. although it also has relevant technical reserves, it has not made any major moves in the foplp field for now.

it is worth mentioning that tsmc has begun to expand its existing packaging plants on a large scale due to full orders, and is even willing to purchase packaging plants from other companies at high prices to meet customer needs.

in august this year, tsmc announced that it had purchased innolux's 5.5-generation panel plant (nanjing fab 4) and its affiliated facilities for approximately us$528 million, and the transaction was scheduled to be completed in november. according to the announcement, the plant's building area is approximately equivalent to more than 96,000 square meters. it is understood that the two parties are negotiating to purchase not only nanjing fab 4, but two plants, and it is rumored that the next transaction may be innolux's nanjing fab 5.

the equipment procurement list issued by tsmc has the number ap 8, which means that after the construction of two packaging plants at ap 7 in chiayi, innolux's old plant in southern taiwan science park will be the next advanced packaging base, and it is planned to start installation in the first quarter of next year. according to the schedule, it may be put into operation earlier than the new chiayi plant to support the most needed cowos production capacity; for the subsequent second plant, innolux may intend to cooperate with tsmc on foplp.

for large manufacturers, foplp has become a battleground, but for ai chips, this packaging technology alone is not enough.

glass substrate competition

why does foplp require a glass substrate?

the characteristic of foplp is the use of a larger substrate, but traditional plastic substrates are prone to warping as the number of ics increases and becomes larger. as many packaging manufacturers begin to use large-size substrates, this problem becomes more prominent.

in addition to warping, plastic substrates (organic material substrates) are also approaching their capacity limits, especially their rough surfaces, which will have a negative impact on the inherent performance of ultra-fine circuits. under such circumstances, glass, as a new type of substrate material, has entered the semiconductor industry.

as a new solution, the glass substrate has a smoother surface than the plastic substrate, and the number of openings in the same area is much greater than that on organic materials. it is reported that the spacing between the through holes in the glass core can be less than 100 microns, which can directly increase the interconnection density between chips by 10 times. the increase in interconnection density can accommodate more transistors, thereby achieving more complex designs and more efficient use of space;

at the same time, glass substrates perform better in thermal properties and physical stability, are more heat-resistant, and are not prone to warping or deformation due to high temperatures. in addition, the unique electrical properties of the glass core give it lower dielectric loss, allowing clearer signal and power transmission. compared with abf plastics, the thickness of the glass core substrate can be reduced by about half, and thinning can also improve signal transmission speed and power efficiency.

but glass substrates are not without their drawbacks. glass sheets are typically 100µm or thinner and are susceptible to cracking or shattering due to stress during transportation, handling, and manufacturing, requiring specialized equipment and processes to work with and manage the material.

additionally, a significant hurdle facing glass substrates is the lack of uniform standards for glass substrate size, thickness, and characteristics. unlike silicon wafers, which follow precise global specifications, glass substrates currently lack universally accepted dimensions and characteristics. the lack of standardization complicates the problem of semiconductor factories where manufacturers can change substrates without making major adjustments to the process. closely related is the issue of compatibility, not only between different batches of glass substrates, but also between the substrate and the semiconductor device it supports, with the unique electrical and thermal properties of the glass having to be carefully matched to those of the semiconductor device.

the characteristics of glass substrates have attracted a lot of attention in the industry, but the technical challenges they bring have discouraged many small and medium-sized enterprises, and only a few giants are willing to be the first to try them out.

image source: intel

in september 2023, intel announced one of the industry's first glass substrates for next-generation advanced packaging, which is scheduled to be launched in the second half of this decade, from 2026 to 2030.

“after a decade of research, intel has achieved industry-leading advanced packaging glass substrates,” said babak sabi, intel senior vice president and general manager of assembly and test development. “we look forward to launching these cutting-edge technologies to benefit our key players and foundry customers for decades to come.”

it is understood that 10 years ago, intel invested 1 billion us dollars in its factory in arizona, usa, and established a glass substrate r&d line and supply chain. it has a long history of promoting the next generation of packaging. in the 1990s, it led the industry's transition from ceramic packaging to organic packaging, and was the first to realize halogen and lead-free packaging, and invented advanced embedded chip packaging technology.

samsung soon followed intel's footsteps and joined the competition. at ces 2024 in january 2024, samsung electronics proposed to establish a glass substrate trial production line this year, with the goal of producing trial products in 2025 and achieving mass production in 2026.

in march this year, samsung electronics has started to jointly develop glass substrates with major electronic affiliates such as samsung electro-mechanics and samsung display. samsung electro-mechanics is expected to contribute its proprietary technology in combining semiconductors and substrates, while samsung display will contribute glass technology. it is understood that this is the first time that samsung electronics has jointly conducted glass substrate research with electronic component companies such as samsung electro-mechanics and samsung display.

of course, samsung and intel aren’t the only companies working on next-generation substrate technology.japanese manufacturer ibiden has also joined the glass-based design and development work. skc, a subsidiary of sk group, has established a subsidiary absolux to develop new mass production capabilities. it has established partnerships with companies such as amd, and lg innotek has also stated that glass will be the main material for semiconductor packaging substrates in the future and the company is considering developing glass substrates.

among these manufacturers, the one that deserves the most attention is undoubtedly tsmc.

although tsmc has not mentioned the glass substrate technology before, considering the company's accumulation in the packaging field,it is very likely that they already have relevant technical reserves.according to media reports, the industry has widely rumored that tsmc has restarted the research and development of glass substrates to meet nvidia's future needs for foplp.

in addition, taiwan's semiconductor equipment manufacturers have also started to deploy in advance. titanium, which has cooperated with intel for many years, initiated and assembled relevant supply chains to establish the e-core system alliance of glass substrate suppliers, with the intention of winning orders from intel and tsmc.

for the packaging industry, foplp and glass substrates are like two sides of the same coin. if you want to apply foplp on a large scale, you need a larger packaging substrate, and a larger packaging substrate cannot avoid a glass substrate. as long as the application demand for foplp continues to rise, the mass production of glass substrates will continue to accelerate.

from wafer to panel

in fact, foplp, as a derivative technology of fowlp, did not receive much attention in the early stage. on the one hand, the application products are limited. on the other hand, this technology tests more than just the packaging capabilities of manufacturers. from the perspective of process capabilities, foplp can be seen as a technology of fowlp and printed circuit board processing, which often requires manufacturers from two different industries to work together to achieve the desired effect.

this is why intel and samsung have made the fastest progress in this field.the former has been the leader of the us semiconductor industry for many years and controls most of the us semiconductor supply chain, while the latter is itself a huge group that involves all aspects of semiconductor production and manufacturing and can solve problems more quickly.

they have undoubtedly brought more pressure to tsmc's packaging business. as foplp and glass substrates gradually mature, it is hard to guarantee that manufacturers like nvidia and amd will switch to other packaging manufacturers for technical reasons.

in addition, the rise of foplp and glass substrates has also allowed us to see more opportunities for panel-level packaging. since both technologies use similar panel sizes, they complement each other in terms of increasing chip density, reducing costs and improving manufacturing efficiency. the future packaging industry is very likely to develop in this direction.

after they redefine the advanced packaging landscape, who will reap the biggest benefits?