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it home reported on september 10 that rambus issued a press release today (september 10), announcing the launch of the industry's first hbm4 memory controller ip, providing a variety of advanced feature sets for hbm4 memory to help designers cope with the next generation of ai accelerators and graphics processing units (gpus).

it home quoted an official press release that rambus's hbm4 controller ip not only supports the 6.4 gbps transmission rate in the jedec specification, but also supports a data transmission rate of up to 10 gbps, providing a data throughput of 2.56 terabytes per second (tb/s) for each memory device.

rambus hbm4 controller ip can be combined with third-party or customer-owned phy solutions to build a complete hbm4 memory subsystem.

	HBM4 Product Brief	HBM3E/3 Product Brief	HBM2E/2 Product Brief
Speed Bins (Gb/s)	Up to 10	Up to 9.6/8.4	Up to 3.6/2.0
Channel Densities (Gb)	Up to 32	Up to 32	Up to 24
Channels | Pseudo-Channels	32	16 | 32	8 | 16
DRAM Stacks	Up to 16	Up to 16	Up to 12
PHY Interface	DFI Style	DFI Style	DFI Style
PHY Independent Mode	Yes	Yes	Yes
Refresh Management Support	Yes	Yes
Look-Ahead Command Processing for Minimum Latency	Yes	Yes	Yes
Integrated Reorder Functionality	Yes	Yes	Add-on core
Self-refresh and Power-down Low Power Modes	Yes	Yes	Yes
RAS Features	Yes	Yes	Yes
Built-in Activity Monitor	Yes	Yes	Yes
DFI Compatible	Yes	Yes	Yes
End-to-end Data Parity	Yes	Yes	Yes
Interface to Logic	Native or AXI	Native or AXI	Native or AXI

neeraj paliwal, senior vice president and general manager of rambus, said:

with the parameter size of large language models (llms) now exceeding trillions and continuing to grow, overcoming the bottleneck of memory bandwidth and capacity is critical to meeting the real-time performance requirements for training and inference ai.

we are bringing the industry's first hbm4 controller ip solution to market to help customers achieve breakthrough performance in their most advanced processors and accelerators.